This technology relates to a semiconductor device wherein a plurality of substrates are bonded to each other to carry out joining between electrodes or wiring lines, a fabrication method for the semiconductor device and an electronic apparatus including the semiconductor device.
A technique of bonding two wafers or substrates to each other to join joining electrodes formed on the semiconductor substrates to each other has been developed already and is disclosed, for example, in Japanese Patent Laid-Open No. 2000-299379.
Further, as one of structures for achieving higher integration of semiconductor devices, a three-dimensional structure wherein two substrates on which elements and wiring lines are formed are laminated and bonded to each other has been proposed. When a semiconductor device of such a three-dimensional structure as just described is to be fabricated, two substrates on which elements are formed are prepared first, and the electrodes for joining, that is, bonding pads, are led out to the bonding face side of the substrates. Thereupon, for example, an embedded wiring technique called damascene technique is applied to form a bonding face configured such that the electrodes for joining made of copper (Cu) are surrounded by an insulating film. Thereafter, the two substrates are disposed with the bonding faces thereof opposed to each other and then are laminated such that the electrodes provided on the bonding faces thereof correspond to each other, and in this state, heat treatment is carried out. Bonding of the substrates between which the electrodes are joined together is carried out thereby. For the fabrication method described, refer to, for example, Japanese Patent Laid-Open No. 2006-191081 (hereinafter referred to as Patent Document 1).
Formation of electrodes by a general embedded wiring technique is carried out, for example, in the following manner. First, a groove pattern is formed on an insulating film which covers the surface of a substrate, and then a conductive base layer or barrier metal layer having a barrier property with respect to copper (Cu) is formed on the insulating film in such a state that it covers an inner wall of the groove pattern. Then, an electrode film for which copper (Cu) is used is formed on the barrier metal layer in such a state that the groove pattern is filled up, and then the electrode film is polished until the barrier metal layer is exposed. Further, the barrier metal layer and the electrode film are polished until the insulating film is exposed. Consequently, an embedded electrode wherein an electrode film is embedded in the groove pattern formed in the insulating film with the barrier metal layer interposed therebetween is formed.
With the foregoing embedded wiring technique, polishing of the electrode film can be stopped automatically at a point of time at which the electrode film is polished until the barrier metal layer is exposed. However, in polishing of the electrode film and the barrier metal layer which is carried out subsequently, the polishing of the electrode film cannot be stopped automatically at a point of time at which the insulating film is exposed. Therefore, in a polishing face, dishing wherein the electrode film in the groove pattern is polished excessively or erosion wherein the electrode film in the groove pattern is polished excessively depending upon an electrode layout are liable to occur, and it is difficult to obtain a flat polished face. Therefore, a method wherein, before the electrode film is formed, the barrier metal layer on the insulating film is removed such that the barrier metal layer remains only on the inner face of the groove pattern and then an electrode film is formed on the remaining barrier metal layer and then polished. The method is disclosed, for example, in Japanese Patent Laid-Open No. 2000-12540 (hereinafter referred to as Patent Document 2).